In static random access memories (SRAMs), there has been an increased need for high speed writing as reading has gotten increasingly faster. With precharging and equalization techniques triggered from address transitions becoming common, access times have been further enhanced. As the read access times have become faster, the need for a faster write has become more significant. Write drivers have typically been push-pull N channel transistors which take advantage of the higher mobility of N channel devices which results in higher gain for a given device size. To increase write speed, the device sizes can simply be increased. Increasing the device size not only increases chip area, but also increases power consumption. With CMOS technology, power consumption can be quite low so that simply increasing the device size to increase speed can result in consuming more power than is desirable.